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NS ESI G W D TS NE D UC FO R DED UTE PRO 6614B) EN M M B S TI T I SL E CO U a nd Data Sheet OT R SIBLE S 6614A, N POS 6014, ISL (ISL6
(R)
HIP6602
August 2000 FN4838.1
Dual Channel Synchronous-Rectified Buck MOSFET Driver
The HIP6602 is a high frequency, two power channel MOSFET driver specifically designed to drive four power N-Channel MOSFETs in a synchronous-rectified buck converter topology. These drivers combined with a HIP63xx series of Multi-Phase Buck PWM controller and Intersil's UltraFETs(R) form a complete core voltage regulator solution for advanced microprocessors. The HIP6602 drives both upper and lower gates over a range of 5V to 12V. This drive-voltage flexibility provides the advantage of optimizing applications involving trade-offs between switching losses and conduction losses. The output drivers in the HIP6602 have the capacity to efficiently switch power MOSFETs at high frequencies. Each driver is capable of driving a 3000pF load with a 30ns propagation delay and 50ns transition time. This device implements bootstrapping on the upper gates with only a single external capacitor required for each power channel. This reduces implementation complexity and allows the use of higher performance, cost effective, N-Channel MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously.
Features
* Drives Four N-channel MOSFETs * Adaptive Shoot-Through Protection * Internal Bootstrap Devices * Supports High Switching Frequency - Fast Output Rise Time - Propagation Delay 30ns * Small 14-Lead SOIC Package * 5V to 12V Gate-Drive Voltages for Optimal Efficiency * Three-State Input for Bridge Shutdown * Supply Under-Voltage Protection
Applications
* Core Voltage Supplies for Intel Pentium(R) III and AMD(R) AthlonTM Microprocessors. * High Frequency Low Profile DC/DC Converters * High Current Low Voltage DC/DC Converters
Pinout
HIP6602CB (SOIC) TOP VIEW
PWM1 PWM2 GND 1 2 3 14 VCC 13 PHASE1 12 UGATE1 11 BOOT1 10 BOOT2 9 UGATE2 8 PHASE2
Ordering Information
PART NUMBER HIP6602CB HIP6602CB-T TEMP. RANGE (C) 0 to 85 PACKAGE 14 Ld SOIC PKG. NO. M14.15
14 Ld SOIC Tape and Reel
LGATE1 4 PVCC PGND LGATE2 5 6 7
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright (c) Intersil Corporation 2000, 2005 Pentium(R) is a registered trademark of Intel Corporation.; AMD(R) is a registered trademark of Advanced Micro Devices, Inc. UltraFET(R) is a registered trademark of Intersil Corporation. AthlonTM is a trademark of Advanced Micro Devices, Inc.
HIP6602 Block Diagram
PVCC BOOT1 UGATE1 VCC +5V SHOOTTHROUGH PROTECTION PHASE1
10K PWM1
PVCC
10K
LGATE1
PGND +5V CONTROL LOGIC PVCC
PGND BOOT2 UGATE2
10K PWM2
10K GND
SHOOTTHROUGH PROTECTION
PHASE2
PVCC
HIP6602
PGND
LGATE2
Typical Application - 2 Channel Converter Using a HIP6302 and a HIP6602 Gate Driver
+5V +12V BOOT1 +12V FB VSEN UGATE1 VCC VCC ISEN1 PGOOD PWM1 MAIN CONTROL HIP6302 PWM1 DUAL DRIVER HIP6602 LGATE1 +VCORE +5V/12V PHASE1
COMP
PVCC
VID
BOOT2
+12V
PWM2 ISEN2
PWM2
UGATE2 PHASE2 LGATE2
FS/DIS
GND GND PGND
2
HIP6602 Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602 Gate Driver
+12V
BOOT1
+12V
UGATE1 VCC PHASE1
LGATE1 +5V
DUAL DRIVER HIP6602
FB VSEN COMP VCC
PVCC
+5V/12V
BOOT2
+12V
UGATE2 ISEN1 PGOOD EN PWM1 PWM2 PWM1 PWM2 LGATE2 PHASE2
VID
MAIN CONTROL HIP6303
ISEN2 GND
PGND
+VCORE ISEN3 FS/DIS PWM3 PWM4 GND ISEN4 UGATE3 VCC PHASE3 +12V BOOT3 +12V
LGATE3
DUAL DRIVER HIP6602
PVCC +5V/12V BOOT4 +12V
UGATE4 PWM3 PWM4 LGATE4 PHASE4
GND
PGND
3
HIP6602
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V BOOT Voltage (VBOOT - VPHASE) . . . . . . . . . . . . . . . . . . . . . . .15V Input Voltage (VPWM) . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V UGATE. . . . . . . . . . . . . . . . . . . . . . VPHASE - 0.3V to VBOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VPVCC + 0.3V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V
Thermal Information
Thermal Resistance (Note 1) JA (C/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Operating Conditions
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0C to 85C Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V 10% Supply Voltage Range PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current Power Supply Current POWER-ON RESET VCC Rising Threshold VCC Falling Threshold PWM INPUT Input Current PWM Rising Threshold PWM Falling Threshold UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC IPVCC
fPWM = 500kHz, VPVCC = 12V fPWM = 500kHz, VPVCC = 12V
-
3.7 2.0
5.0 4.0
mA mA
9.7 9.0
9.95 9.2
10.4 9.5
V V A V V ns ns ns ns ns ns V ns mA mA
IPWM
VPWM = 0 or 5V (See Block Diagram) VPVCC = 12V VPVCC = 12V
3.45 1.4 -
500 3.6 1.45 20 50 20 20 30 20 230
1.55 3.6 -
TRUGATE TRLGATE TFUGATE TFLGATE
VPVCC = VVCC = 12V, 3nF Load VPVCC = VVCC = 12V, 3nF Load VPVCC = VVCC = 12V, 3nF Load VPVCC = VVCC = 12V, 3nF Load
UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay Shutdown Window Shutdown Holdoff Time OUTPUT Upper Drive Source Impedance
TPDLUGATE VPVCC = VVCC = 12V, 3nF Load TPDLLGATE VPVCC = VVCC = 12V, 3nF Load
RUGATE RUGATE ILGATE RLGATE
VVCC = 12V, VPVCC = 5V VVCC = VPVCC = 12V VVCC = 12V, VPVCC = 5V VVCC = VPVCC = 12V VVCC = 12V, VPVCC = 5V VVCC = VPVCC = 12V VVCC = 12V, VPVCC = 5V or 12V
400 500 -
1.7 3.0 2.3 1.1 580 730 1.6
3.0 5.0 4.0 2.0 4.0
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Sink Impedance
4
HIP6602 Functional Pin Descriptions
PWM1 (Pin 1) and PWM2 (Pin 2)
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see the three-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM output of the controller. PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFETs. See the Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the appropriate capacitor value.
VCC (Pin 14)
Connect this pin to a +12V bias supply. Place a high quality bypass capacitor from this pin to GND. To prevent forward biasing an internal diode, this pin should be more positive then PVCC during converter start-up.
GND (Pin 3)
Bias and reference ground. All signals are referenced to this node.
LGATE1 (Pin 4) and LGATE2 (Pin 7)
Lower gate drive outputs. Connect to gates of the low-side power N-Channel MOSFETs.
Description
Operation
Designed for versatility and speed, the HIP6602 two channel, dual MOSFET driver controls both high-side and low-side N-Channel FETs from two externally provided PWM signals. The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [TPDLLGATE], the lower gate begins to fall. Typical fall times [TFLGATE] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [TPDHUGATE] based on how quickly the LGATE voltage drops below 1.0V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [TRUGATE] and the upper MOSFET turns on.
PVCC (Pin 5)
This pin supplies the upper and lower gate drivers bias. Connect this pin from +12V down to +5V.
PGND (Pin 6)
This pin is the power ground return for the lower gate drivers.
PHASE2 (Pin 8) and PHASE1 (Pin 13)
Connect these pins to the source of the upper MOSFETs and the drain of the lower MOSFETs. The PHASE voltage is monitored for adaptive shoot-through protection. These pins also provide a return path for the upper gate drive.
UGATE2 (Pin 9) and UGATE1 (Pin 12)
Upper gate drive outputs. Connect to gate of high-side power N-Channel MOSFETs.
BOOT 2 (Pin 10) and BOOT 1 (Pin 11)
Floating bootstrap supply pins for the upper gate drivers. Connect the bootstrap capacitor between these pins and the
Timing Diagram
PWM
TPDHUGATE
TPDLUGATE TRUGATE
TFUGATE
UGATE LGATE
TFLGATE TPDLLGATE TPDHLGATE
TRLGATE
5
HIP6602
A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [TPDLUGATE] is encountered before the upper gate begins to fall [TFUGATE]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, TPDHLGATE. The PHASE voltage is monitored and the lower gate is allowed to rise after PHASE drops below 0.5V. The lower gate then rises [TRLGATE], turning on the lower MOSFET. The bootstrap capacitor must have a maximum voltage rating above PVCC + 5V. The bootstrap capacitor can be chosen from the following equation:
Q GATE C BOOT ----------------------V BOOT
Where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose a HUF76139 is chosen as the upper MOSFET. The gate charge, QGATE , from the data sheet is 65nC for a 10V upper gate drive. We will assume a 200mV droop in drive voltage over the PWM cycle. We find that a bootstrap capacitance of at least 0.325F is required. The next larger standard value capacitance is 0.33F.
Three-State PWM Input
A unique feature of the HIP6602 drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled.
Gate Drive Voltage Versatility
The HIP6602 provides the user flexibility in choosing the gate drive voltage. Simply applying a voltage from 5V up to 12V on PVCC will set both driver rail voltages.
Adaptive Shoot-Through Protection
The drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to rise. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1.0V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the PHASE voltage during UGATE turn-off. Once PHASE has dropped below a threshold of 0.5V, the LGATE is allowed to rise. If the PHASE does not drop below 0.5V within 250ns, LGATE is allowed to rise. This is done to generate the bootstrap refresh signal. PHASE continues to be monitored during the lower gate rise time. If the PHASE voltage exceeds the 0.5V threshold during this period and remains high for longer than 2s, the LGATE transitions low. This is done to make the lower MOSFET emulate a diode. Both upper and lower gates are then held low until the next rising edge of the PWM signal.
Power Dissipation
Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125C. The maximum allowable IC power dissipation for the 14 lead SOIC package is approximately 1000mW. Improvements in thermal transfer may be gained by increasing the PC board copper area around the HIP6602. Adding a ground pad under the IC to help transfer heat to the outer peripheral of the board will help. Also keeping the leads to the IC as wide as possible and widening this these leads as soon as possible to further enhance heat transfer will also help. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired frequency for the selected MOSFETs. The total chip power dissipation is approximated as:
_ P = 1.05 x fSW x VPVCC [3 (QU1 + QU2) + (QL1 + QL2)] + IDDQ x VCC 2
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored and gate drives are held low until a typical VCC rising threshold of 9.95V is reached. Once the rising VCC threshold is exceeded, the PWM input signal takes control of the gate drives. If VCC drops below a typical VCC falling threshold of 9.2V during operation, then both gate drives are again held low. This condition persists until the VCC voltage exceeds the VCC rising threshold.
where fsw is the switching frequency of the PWM signal. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The IDDQ VCC product is the quiescent power of the driver and is typically 40mW. The 1.05 term is a correction factor derived from the following characterization. The base circuit for characterizing the drivers for different loading profiles and frequencies is provided. CU and CL are the upper and lower gate load capacitors. Decoupling capacitors [0.15F] are added to the
Internal Bootstrap Device
Both drivers feature an internal bootstrap device. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit.
6
HIP6602
PVCC and VCC pins. The bootstrap capacitor value in the test circuit is 0.01F. The power dissipation approximation is a result of power transferred to and from the upper and lower gates. But, the internal bootstrap device also dissipates power on-chip during the refresh cycle. Expressing this power in terms of the upper MOSFET total gate charge is explained below. The bootstrap device conducts when the lower MOSFET or its body diode conducts and pulls the PHASE node toward GND. While the bootstrap device conducts, a current path is formed that refreshes the bootstrap capacitor. Since the upper gate is driving a MOSFET, the charge removed from the bootstrap capacitor is equivalent to the total gate charge of the MOSFET. Therefore, the refresh power required by the bootstrap capacitor is equivalent to the power used to charge the gate capacitance of the upper MOSFETs.
P REFRESH = f SW Q V = f SW Q V LOSS PVCC U PVCC
PGND
tied together and to a +12V supply. Figures 5 through 7 show the same characterization for PVCC tied to +5V instead of +12V. The gate supply voltage, PVCC, within the HIP6602 sets both upper and lower gate driver supplies at the same 5V level for the last three curves.
Test Circuit
+5V OR +12V +12V +5V OR +12V 0.01F PVCC 0.15F BOOT1 2N7002 UGATE1 PHASE1 VCC 0.15F PWM1 HIP6602 LGATE1 2N7002 CL 100k CU
where QLOSS is the total charge removed from the bootstrap capacitors and provided to the upper gate loads. In Figure 1, CU and CL values are the same and frequency is varied from 10kHz to 2MHz. PVCC and VCC are tied together to a +12V supply. Figure 2 shows the dissipation in the driver with 1nF loading on both gates and each individually. Figure 3 is the same as Figure 2 except the capacitance is increased to 3nF. The impact of loading on power dissipation is shown in Figure 4. Frequency is held constant while the gate capacitors are varied from 1nF to 5nF. VCC and PVCC are
0.01F BOOT2 2N7002 UGATE2 CU
GND
PWM2
PHASE2
LGATE2 2N7002 CL 100k
Typical Performance Curves
1200 1000 800 600 400 200 0 0 500 1000 1500 FREQUENCY (kHz) CU = CL = 2nF CU = CL = 1nF 200 0 0 500 1000 FREQUENCY (kHz) 1500 2000 CU = C L = 5nF CU = C L = 4nF CU = C L = 3nF PVCC = 12V VCC = 12V POWER (mW) 1200 PVCC = VCC = 12V 1000 CU = CL = 1nF 800 CL = 1nF, CU = 0nF 600 400 CU = 1nF, CL = 0nF
POWER (mW)
FIGURE 1. POWER DISSIPATION vs FREQUENCY
FIGURE 2. 1nF LOADING PROFILE
7
HIP6602 Typical Performance Curves
1200 PVCC = VCC = 12V 1000 1000 CU = CL = 3nF POWER (mW) 800 600 400 200 0 0 500 1000 1500 FREQUENCY (kHz) POWER (mW) 800 600 200kHz 400 100kHz 200 30kHz 0 1 2 3 4 5 GATE CAPACITANCE (CU = CL ), (nF) 10kHz 500kHz PVCC = VCC = 12V
(Continued)
1200
CU = 3nF, CL = 0nF CL = 3nF, CU = 0nF
FIGURE 3. 3nF LOADING PROFILE
FIGURE 4. POWER DISSIPATION vs LOADING
800 PVCC = 5V, VCC = 12V 700 600 POWER (mW) 500 400 300 200 CU = CL =1nF 100 0 0 500 1000 FREQUENCY (kHz) 1500 2000 CU = CL = 2nF CU = CL = 3nF POWER (mW) CU = CL = 5nF CU = CL = 4nF
350 PVCC = 5V, VCC = 12V 300 CU = CL = 1nF 250 200 150 CU = 1nF, CL = 0nF 100 50 0 CL = 1nF, CU = 0nF
0
500
1000 FREQUENCY (kHz)
1500
2000
FIGURE 5. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
FIGURE 6. POWER DISSIPATION vs FREQUENCY, PVCC = 5V
600 PVCC = 5V, VCC = 12V 500 1.5MHz 2MHz POWER (mW) 400 1MHz
300 500kHz 200 100kHz 200kHz 100 0 30kHz 1 2 3 4 GATE CAPACITANCE (CU = CL), (nF) 5
FIGURE 7. POWER DISSIPATION vs LOADING, PVCC = 5V
8
HIP6602 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M14.15 (JEDEC MS-012-AB ISSUE C)
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 8.55 3.80 MAX 1.75 0.25 0.51 0.25 8.75 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.3367 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.3444 0.1574
A1 B C D E
A1 0.10(0.004) C
e
B 0.25(0.010) M C AM BS
e H h L N
0.050 BSC 0.2284 0.0099 0.016 14 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 14 0o 6.20 0.50 1.27
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 9

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